Microprocessor

1. Memory Banking

1.1. High level(ODD Bank)

1.1.1. 0001,0003,0005.....

1.2. Low Level (EVEN Bank)

1.2.1. 0000,0002,0004.....

2. Segmentation

2.1. Code Segment (CS) Register

2.1.1. Instruction pointer(IP)

2.2. Data Segment(DS) Register

2.2.1. Source Index(SI)

2.3. Stack Segment(SS) Register

2.3.1. Stack Pointer(SP)

2.3.2. Base Pointer(BP)

2.4. Extra Segment(ES) Register

2.4.1. Destination Index(DI)

3. General Purpose Register

3.1. AX Register

3.1.1. AL Register

3.1.2. AH Register

3.2. BX Register

3.2.1. BL Register

3.2.2. BH Register

3.3. CX Register

3.3.1. CL Register

3.3.2. CX register

3.4. DX Register

3.4.1. DL register

3.4.2. DX Register

4. Architecture

4.1. BIU(bus Interface Unit)

4.1.1. Special Purpose Register/Instruction pointer

4.1.2. 6 byte Instruction Queue

4.1.3. Arithmetic circuit

4.2. EU(Execution Unit)

4.2.1. Control System

4.2.2. ALU(Arithmetic Logical Unit)

4.2.3. General Purpose Register

4.2.4. Flag Register

4.2.5. Operands

5. Flag Register

5.1. Status Flag

5.1.1. Carry flag

5.1.2. Auxilary falg

5.1.3. Parity flag

5.1.4. Sign flag

5.1.5. Over flow flag

5.1.6. Zero flag

5.2. Control Flag

5.2.1. Trap flag

5.2.2. Direction flag

5.2.3. Interrupt flag

6. Pipelining

6.1. Fetch Instruction

6.2. Execute Instruction