1. Dynamic RAM (DRAM) - Made with cells that store data as charge on capacitors - Presence or absence of charge in a capacitor is interpreted as a binary 1 or 0. - Requires periodic charge refreshing to maintain data storage - The term dynamic refers to tendency of the stored charge to leak away, even with power continuously applied
2. DRAM vs SRAM - Both volatile - Dynamic cell - Static
3. Static RAM (SRAM) - Digital device that uses the same logic elements used in the processor - Binary values are stored using traditional flip-flop logic gate configurations - Will hold its data as long as power is supplied to it
4. Programmable ROM (PROM) - Less expensive alternative Nonvolatile and may be written into only once - Writing process is performed electrically and may be performed by supplier or customer at a time later than the original chip fabrication - Special equipment is required for the writing process - Provides flexibility and convenience - Attractive for high volume production runs
5. Read-Mostly Memory
5.1. erasable programmable read-only memory (EPROM)
5.2. electrically erasable programmable read-only memory (EEPROM).
5.3. flash memory
6. Interleaved Memory
6.1. Composed of a collection of DRAM chips.
6.2. Grouped together to form a memory bank.
6.3. Each bank is independently able to service a memory read or write request.
6.4. K banks can service K requests simultaneously, increasing memory read or write rates by a factor of K.
6.5. If consecutive words of memory are stored in different banks, the transfer of a block of memory is speeded up.
7. Hamming Error Detection
7.1. Syndrome Word
7.1.1. To start, determine how long the code must be. A bit by bit comparison is done by taking the exclusive-OR of two inputs. The result is called the syndrome word. Each bit of the syndrome is 0 or 1 according to if there is or is not a match in that bit position for the two inputs. The syndrome word is K bits wide and has a range between 0 and 2K-1. The value 0 indicates that no error was detected, leaving 2K-1 values to indicate if there is an error, which bit was in error. Because an error could occur on any of the M data bits or K check bits, we must have 2^𝐾−1≥𝑀+𝐾 If a word M has 8 data bits, K would be 4 bits. Thus, eight data bits require four check bits.
7.1.2. For convenience, to generate a 4-bit syndrome for an 8-bit data word, the following characteristics is required: If the syndrome contains all 0s, no error has been detected If the syndrome contains one and only one bit set to 1, then an error has occurred in one of the check bits. No correction is needed. If the syndrome contains more than one bit set to 1, then the numerical value of the syndrome indicates the position of the data bit in error. This data bit is inverted for correction. To achieve this, the data and check bits are arranged into a 12-bit word. The bit positions are numbered from 1 to 12. Those bit positions whose position numbers are powers of 2 are designated as check bits.
7.2. Check Bits
7.2.1. The check bits are calculated as follows, where the symbol ⨁ designates the exclusive-OR operation:- C1 = D1 ⨁ D2 ⨁ D4 ⨁ D5 ⨁ D7 C2 = D1 ⨁ D3 ⨁ D4 ⨁ D6 ⨁ D7 C4 = D2 ⨁ D3 ⨁ D4 ⨁ D8 C8 = D5 ⨁ D6 ⨁ D7 ⨁ D8 Each check bit operates on every data bit whose position number contains a 1 in the same bit position as the position number of that check bit.
8. Read Only Memory (ROM) - Contains a permanent pattern of data that cannot be changed or added to - No power source is required to maintain the bit values in memory - Data or program is permanently in main memory and never needs to be loaded from a secondary storage device - Data is actually wired into the chip as part of the fabrication process - Disadvantages of this: - No room for error, if one bit is wrong the whole batch of ROMs must be thrown out - Data insertion step includes a relatively large fixed cost
9. Error Correction
9.1. Hard Failure
9.1.1. - Permanent physical defect - Memory cell or cells affected cannot reliably store data but become stuck at 0 or 1 or switch erratically between 0 and 1 - Can be caused by: - Harsh environmental abuse - Manufacturing defects - Wear
9.2. Soft Error
9.2.1. - Random, non-destructive event that alters the contents of one or more memory cells - No permanent damage to memory - Can be caused by: - Power supply problems - Alpha particles
10. Advanced DRAM Organization - One of the most critical system bottlenecks when using high-performance processors is the interface to main internal memory - The traditional DRAM chip is constrained both by its internal architecture and by its interface to the processor’s memory bus - A number of enhancements to the basic DRAM architecture have been explored. - The schemes that currently dominate the market are SDRAM and DDR-DRAM.
10.1. Synchronous DRAM (SDRAM)
10.1.1. One of the most widely used forms of DRAM
10.1.2. Exchanges data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states
10.1.3. With synchronous access the DRAM moves data in and out under control of the system clock - The processor or other master issues the instruction and address information which is latched by the DRAM - The DRAM then responds after a set number of clock cycles - Meanwhile the master can safely do other tasks while the SDRAM is processing
10.2. Rambus DRAM
10.2.1. Developed by Rambus
10.2.2. Adopted by Intel for its Pentium and Itanium processors
10.2.3. Has become the main competitor to SDRAM
10.2.4. Chips are vertical packages with all pins on one side
10.2.5. Bus can address up to 320 RDRAM chips and is rated at 1.6 GBps
10.2.6. Bus delivers address and control information using an asynchronous block-oriented protocol
10.3. Cache DRAM
10.3.1. Developed by Mitsubishi
10.3.2. Integrates a small SRAM cache onto a generic DRAM chip
10.3.2.1. It can be used as a true cache consisting of a number of 64-bit lines. Cache mode of the CDRAM is effective for ordinary random access to memory
10.3.2.2. Can also be used as a buffer to support the serial access of a block of data