DEE20033 Digital Electronics

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DEE20033 Digital Electronics by Mind Map: DEE20033 Digital Electronics

1. Final Exam

1.1. Structure (80m)

1.1.1. Number and codes (T1)

1.1.2. Boolean Operation (T2)

1.1.3. Flip-flops (T3)

1.1.4. Registers (T5)

1.2. Essay(20m)

1.2.1. Counters (T4)

2. Continuous Assessment (CA)

2.1. Quiz (2)

2.1.1. 5%

2.2. Theory Test (1)

2.2.1. 10%

2.3. Practical Work (6)

2.3.1. 25%

2.4. Practical Test (1)

2.4.1. 5%

2.5. Practical Work (Generic Scill)

2.5.1. 5%

2.6. EOC (1)

2.6.1. 10%

3. CLO

3.1. Apply the knowledge of logic operations using Boolean Algebra or Karnaugh Map in digital logic circuit ( C3 , PLO 1 )

3.2. Construct the logic diagrams, truth tables and timing diagrams using logic gates and flip-flop ( P4 , PLO 5 )

3.3. Demonstrate ability to work in team to complete assigned task during practical work sessions ( A3 , PLO 9 )

4. Sub Topics

4.1. Numbers & Codes

4.1.1. Numbers

4.1.1.1. DECIMAL

4.1.1.1.1. N10-N2,8,16

4.1.1.2. BINARY

4.1.1.2.1. N2-N8,10,16

4.1.1.3. OCTAL

4.1.1.3.1. N8-N2,10,16

4.1.1.4. HEXADECIMAL

4.1.1.4.1. N16-N2,10,8

4.1.2. Codes

4.1.2.1. BCD

4.1.2.1.1. BCD-N10-N2

4.1.2.2. ASCII

4.1.2.3. GRAY

4.1.2.3.1. GRAY-N2

4.1.3. Arithmetics

4.1.3.1. Addition

4.1.3.2. Substract

4.1.4. Complements

4.1.4.1. 1st complement

4.1.4.2. 2nd complement

4.2. Boolean Operation

4.2.1. Gates

4.2.1.1. Basic Gates

4.2.1.1.1. NOT

4.2.1.1.2. AND

4.2.1.1.3. OR

4.2.1.2. Universal Gates

4.2.1.2.1. NOR

4.2.1.2.2. NAND

4.2.1.2.3. EX OR

4.2.1.2.4. EX NOR

4.2.2. Draw logic circuit using NAND gate

4.2.3. Logic Circuit

4.2.3.1. SOP

4.2.3.2. POS

4.2.4. Simplified

4.2.4.1. Boolean

4.2.4.2. K-Maps

4.2.4.3. De' Morgan

4.3. FLip-Flops

4.3.1. Asychronous

4.3.1.1. SR Flip-Flops

4.3.1.1.1. SR NOR

4.3.1.1.2. SR NAND

4.3.2. Sycnhronous

4.3.2.1. Clocked SR

4.3.2.2. JK

4.3.2.3. D

4.3.2.4. T

4.3.2.5. JK with Preset & Clr

4.3.3. Application

4.3.3.1. Memory

4.3.3.2. Logic Controller

4.3.3.3. Counter

4.3.3.4. Register

4.4. Counters

4.4.1. Asynchronous

4.4.1.1. Up Counter

4.4.1.2. Down Counter

4.4.1.3. Up/Down Counter

4.4.1.4. Decade Counter

4.4.1.5. Modulo <2n

4.4.2. Synchronous

4.4.2.1. Up Counter

4.4.2.2. Down Counter

4.4.2.3. Up/Down Counter

4.4.2.4. Random Counter

4.4.3. Cascade

4.4.4. Application

4.5. Registers

4.5.1. Types

4.5.1.1. Series in Series Out (SISO)

4.5.1.2. Series in Parallel Out (SIPO)

4.5.1.3. Parallel In Parallel Out (PIPO)

4.5.1.4. Parallel In Series Out (PISO)

4.5.2. Application

4.5.2.1. Arithmetic

4.5.2.1.1. Multiplier

4.5.2.1.2. Divider

4.5.2.2. Counter

4.5.2.2.1. Ring Counter

4.5.2.2.2. Johnson Counter

5. References

5.1. Neal S. Widmer, Gregory L. Moss, Ronald J. Tocci (2017). Digital Systems-Principles and Applications (12th ed.). Pearson Higher Ed USA

5.2. Dr. Sanjay Sharma (2017). Digital Electronics and Logic Design. S.K.Kataria & Sons

5.3. Dr. B.R. Gupta, V. Singhal (2018). Digital Electronics. S.K. Kataria & Sons

5.4. Floyd ,L.Thomas (2014). Digital Fundamentals (11th ed.).Pearson Education International

5.5. Pratima Manhas, Shaveta Thakral (2015). Digital Electronics. S.K.Kataria & Sons

6. PLO

6.1. PLO1: apply knowledge of applied mathematics, applied science, engineering fundamentals and an engineering specialisation as specified in DK1 to DK4 respectively to wide practical procedures and practices

6.2. PLO5: apply appropriate techniques, resources, and modern engineering and IT tools to well-defined engineering problems, with an awareness of the limitations (DK6)

6.3. PLO9: function effectively as an individual, and as a member in diverse technical teams