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Rocket clouds
CompArch by Mind Map: CompArch

1. Caches

1.1. Direct mapped

1.2. valid bit

1.3. select byte

1.4. a,b,c

1.5. write through vs write back

1.6. locality of reference

1.7. Set associative cache

2. memory

2.1. Direct Memory Access

2.2. Harvard/von Neumann

3. instruction pipeline

4. instruction sets

5. RISC vs CISC

6. Register sets

7. virtual memory

8. Processor vendors

8.1. ARM

8.2. Intel Pentium

8.3. TI MSP 430

9. NAND to TETRIS not examinable

10. Parallel/multi-core/multi-processing/multi-threading

11. Relationship to HLL (e.g. C)