CompArch
by Steven Bradley
1. instruction pipeline
2. instruction sets
3. RISC vs CISC
4. Register sets
5. virtual memory
6. Processor vendors
6.1. ARM
6.2. Intel Pentium
6.3. TI MSP 430
7. NAND to TETRIS not examinable
8. Parallel/multi-core/multi-processing/multi-threading
9. Relationship to HLL (e.g. C)
10. Caches
10.1. Direct mapped
10.2. valid bit
10.3. select byte
10.4. a,b,c
10.5. write through vs write back
10.6. locality of reference
10.7. Set associative cache
11. memory
11.1. Direct Memory Access
11.2. Harvard/von Neumann