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Rocket clouds

1. Dual-Mode Operation

1.1. User Mode

1.1.1. user program executes in user mode

1.1.2. certain instructions may not be executed

1.1.3. certain areas of memory are protected from user access

1.2. When an interrupt or fault occurs, hardware switches to kernel mode.

1.3. Kernel Mode

1.3.1. monitor executes in kernel mode

1.3.2. protected areas of memory may be accessed

1.3.3. privileged instructions may be executed

1.3.4. the software has complete control of the processor and all instruction, registers and memory

2. Storage Structure

2.1. Main memory

2.1.1. volatile storage that only store large storage media that the CPU can access directly but the contents will be lost when power is turned off.

2.2. Secondary storage

2.2.1. non volatile storage that hold large quantities of data permanently.

3. Storage Hierarchy

3.1. Storage System

3.1.1. organized in hierarchy that is speed, cost, and volatilily

3.2. Caching

3.2.1. copying information into faster storage system

4. Memory Protection

4.1. Limit register – contains the size of the range

4.2. Base register – holds the smallest legal physical memory address.

4.3. Memory outside the defined range is protected

5. Hardware Address Protection

5.1. Operating Systems

5.1.1. allowed to load users’ programs into users’ memory, to access and modify parameters of system calls.

6. CPU Protection

6.1. Timer

6.1.1. interrupts computer after specified period to ensure operating system maintains control over CPU Every time the clock ticks, the counter is decremented. When timer reaches the value 0, an interrupt occurs.

6.2. Load-timer is a privileged instruction.

7. I/O Protection

7.1. I/O instructions are privileged instructions; user program cannot issue I/O instructions directly.

7.1.1. User program must execute a system call to request that the operating system to perform I/O.

7.1.2. ensure that a user program could never gain control of the computer in monitor mode i.e a user program, as part of its execution, stores a new address in the interrupt vector.