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1. Immediate Addressing

1.1. Simplest form of addressing

1.2. Operand = A

1.3. This mode can be used to define & use constants or set initial values of variables

1.3.1. Typically the number will be stored in twos complement form

1.3.2. The leftmost bit of the operand field is used as a sign bit

1.4. Advantage:

1.4.1. No memory reference other than the instruction fetch is required to obtain the operand,thus saving one memory or cache cycle in the instruction cycle

1.5. Disadvantage

1.5.1. The size of the number is restricted to the size of the address field,which,in most instruction sets,is small compared with the word length

2. Addressing Modes

2.1. Register Indirect

2.2. Immediate

2.3. Direct

2.4. Indirect

2.5. Register

2.6. Displacement

2.7. Stack

2.8. Direct Addresing

2.8.1. Address field contains the effective address of the operand

2.8.2. Effective address(EA) = address field (A)

2.8.3. Was common in earlier generations of computers

2.8.4. Requires only one memory reference & no special calculation

2.8.5. Limitation is that it provides only a limited address space

2.9. Indirect Addressing

2.9.1. Reference to the address of a word in memory which contains a full-length address of the operand

2.9.2. EA=(A) Parentheses are to be interpreted as meaning contents of

2.9.3. Advantage: For a word length of N an address space of 2^n is now available

2.9.4. Disadvantage: Instruction execution requires two memory references to fetch the operand 1 to get its address & a second to get its value

2.9.5. A rarely used variant of indirect addressing in multilevel or cascaded indirect addressing EA =(...(A)...) Disadvantage is that 3 or more memory references could be required to fetch an operand

2.10. Register Addressing

2.10.1. Address field refers to a register rather than a main memory address

2.10.2. EA=R

2.10.3. Advantages: Only a small address field is needed in the instruction No time-consuming memory references are required

2.10.4. Disadvantage: The address space is very limited

2.11. Register Indirect Addressing

2.11.1. Analogous to indirect addressing The only difference is whether the address field refers to a memory location or a register

2.11.2. EA=(R)

2.11.3. Address space limitation of the address field is overcame by having that field refer to a word-length location containing an address

2.11.4. Uses one less memory reference than indirect addressing

2.12. Displacement Addressing

2.12.1. Combines the capabilities of direct addressing & register indirect addressing

2.12.2. EA=A+(R)

2.12.3. Requires that the instruction have two address fields,at least one of which is explicit The value contained in one address field(value=A) is used The other address field refers to a register whose contents are added to A to produce the effective address

2.12.4. Most common uses: Relative addressing Base-register addressing Indexing

2.13. Relative Addresing

2.13.1. The implicitly referenced register is the program counter(PC) The next instruction address is added to the address field to produce the EA Typically the address field is treated as s twos complement number for this operation Thus the effective address is a displacement relative to the address of the instruction

2.13.2. Exploits the concept of locality

2.13.3. Saves address bits in the instruction if most memory references are relatively near to the instruction being executed

2.14. Base-Register Addressing

2.14.1. The referenced register contains a main memory address & the address field contains a displacement from that address

2.14.2. The register reference may be explicit or implicit

2.14.3. Exploits the locality of memory references

2.14.4. Convenient means of implementing segmentation

2.14.5. In some implementations a single segment base register is employed & is used implicitly

2.14.6. In others the programmer may choose a register to hold the base address of a segment & the instruction must reference it explicitly

2.15. Indexed Addressing

2.15.1. The address field references a main memory address & the reference register contains a positive displacement from that address

2.15.2. The method of calculating the EA is the same as for base-register addressing

2.15.3. An important use is to provide an efficient mechanism for performing iterative operations

2.15.4. Autoindexing Automatically increment or decrement the index register after each reference to it EA=A+(R)

2.15.5. Postindexing Indexing is performed after the indirection EA=(A) +(R)

2.15.6. Preindexing Indexing is performed before the indirection EA =(A +(R))

2.16. Stack Addressing

2.16.1. A stack is a linear array of locations Sometimes referred to as a pushdown list or last-in-first-out queue

2.16.2. A stack is a reserved block of locations items are appended to the top of the stack so that the block is partially filled

2.16.3. Associated with the stack is a pointer whose value is the address of the top of the stack The stack pointer is maintained in a register Thus references to stack locations in memory are in fact register indirect addresses

2.16.4. Is a form of implied addressing

2.16.5. The machine instructions need not include a memory reference but implicitly operate on the top of the stack

3. Instruction Formats

3.1. Define the layout of the bits of an instruction,in terms of its constituent fields

3.2. Must include an opcode and ,implicitly or explicitly,indicate the addressing mode for each operand

3.3. For most instruction sets more than one instruction format is used

3.4. Instruction Length

3.4.1. Most basic design issue

3.4.2. Affects,&is affected by: Memory size Memory organization Bus structure Processor complexity Processor speed

3.4.3. Should be equal to the memory-transfer length or one should be multiple of the other

3.4.4. Should be a multiple of the character length,which is usually 8 bits,and of the length of fixed-point numbers

3.5. Allocation of Bits

3.5.1. Number of addressing modes

3.5.2. Number of operands

3.5.3. Register versus memory

3.5.4. Number of register sets

3.5.5. Address range

3.5.6. Address granularity

3.6. Variable-Length Instructions

3.6.1. Variations can be provided efficiently and compactly

3.6.2. Increases the complexity of the processor

3.6.3. Does not remove the desirability of making all of the instruction lengths integrally related to word length Because the processor does not know the length of the next instruction to be fetched a typical strategy is to fetch a number of bytes or words equal to at least the longest possible instruction Sometimes multiple instructions are fetched