Logic Gates

1. Combinational Logic Circuits

1.1. Adders

1.2. Subtractors

1.3. Multiplexers

1.4. Demultiplexers

1.5. Encoders

1.6. Decoders

2. Flip Flops & Sequential Circuits

2.1. Latch & Flip Flops

2.1.1. SR

2.1.2. JK

2.1.3. Master slave JK

2.1.4. D

2.1.5. T

2.2. Shift Registers

2.2.1. Instruction

2.2.1.1. Addressing mode

2.2.1.1.1. Immediate

2.2.1.1.2. Direct

2.2.1.1.3. Indirect

2.2.1.1.4. Register

2.2.1.1.5. Register Indirect

2.2.1.1.6. Auto-Increment/Decrement mode

2.2.1.1.7. Relative

2.2.1.1.8. Base Register

2.2.1.1.9. Index Register

2.2.1.2. Opcode

2.2.1.2.1. Memory Reference

2.2.1.2.2. Register Reference

2.2.1.2.3. I/O Instructions

2.2.1.3. Address/Operation

2.2.1.3.1. Arithmetic Micro-Operations

2.2.1.3.2. Logical Micro-Operations

2.2.1.3.3. Shift Micro-Operations

2.2.2. SISO

2.2.3. SIPO

2.2.4. PISO

2.2.5. PIPO

2.2.6. Applications

2.2.6.1. Synchronous Counters

2.2.6.2. Asynchronous Counters

2.2.6.3. Divide-by-N Ripple Counters