1. I/O structure
1.1. (a) Synchronous I/O structure
1.1.1. Control return to user program after I/O start upon I/O completion
1.1.1.1. CPU idle while waiting for instruction
1.1.1.2. Wait loop
1.1.1.3. No simultaneous I/o processing
1.2. (b) Asynchronous I/O structure
1.2.1. Control returns to user program without waiting for I/O completion
1.2.1.1. System Call
1.2.1.1.1. Request OS to allow user to wait for I/O completion
1.2.1.2. Device Stauts Table
1.2.1.2.1. Contain each I/O device
1.2.1.2.2. Indicate its type, address and state.
1.3. Contain type and value common to all the input and output structure
2. Storage Structure
2.1. Main memory
2.1.1. CPU can access directly
2.1.2. Volatile
2.2. Secondary memory
2.2.1. Provide non-volatile storage capacity
2.2.2. Capable to hold large qualities of data permanently
2.3. Storage System Hierarchy
2.3.1. Speed
2.3.2. Cost
2.3.3. Volatility
2.3.4. Electronic Disk
2.3.4.1. Normal Operation
2.3.4.1.1. Volatile
2.3.4.2. Power Interrupted
2.3.4.2.1. data copied to non-volatile media
3. Guideline
3.1. Main Topic
3.2. Point
3.3. Description
3.4. Working step
4. Computer System Operation
4.1. General purpose computer system
4.1.1. CPU and device execute concurrently
4.2. Device controller sent interrupt to CPU when finished its operation.
4.2.1. Interrupt indicate the concurrence of an event from either hardware or software
4.2.2. CPU stop current execution
4.2.2.1. CPU store execution to fixed location
4.2.2.1.1. Fixed location contain starting address and ISR.
4.2.2.1.2. Saved return address loaded after interrupt service
4.3. Device Controller
4.3.1. Synchronize the access of memory
4.3.2. Contain local buffer
5. Dual mode operation
5.1. To ensure the proper execution of OS
5.2. User mode Mod bit : (1)
5.2.1. execute user program
5.2.2. Restriction
5.2.2.1. Not executable area of memory
5.2.2.2. Not executable instruction
5.3. Kernel mode Mode bit : (0)
5.3.1. a.k.a. system mode, monitor mode
5.3.2. Privileged instruction may be execute
5.3.3. Protected area of memory can be access
6. Protection of Computer System Software
6.1. I/O protection
6.1.1. All I/O instruction is privileged instruction
6.1.1.1. User program cannot issue directly
6.1.1.1.1. User program executes a system call to request OS to perform I/O
6.1.2. Must ensure user program unable to control computer in monitor mode
6.2. Memory protection
6.2.1. Computer system must provide protection at least for interrupt vector and ISR.
6.2.1.1. Memory beyond the defined range is protected
6.2.2. Two register are used
6.2.2.1. To determine the range of legal address
6.2.2.2. Base Register
6.2.2.2.1. Hold smallest legal physical memory address
6.2.2.3. Limit Register
6.2.2.3.1. Contain the size of range
6.3. Hardware address protection
6.3.1. Load instruction for the base register and limit register are privileged instruction
6.4. CPU protection
6.4.1. Timer
6.4.1.1. Interrupt CPU after specified period
6.4.1.1.1. Ensure OS maintain control over CPU
6.4.1.2. Every time clock ticks, COunter decremented
6.4.1.2.1. When Timer reach value 0, interrupt occur
6.4.2. Load timer is privileged instruction