MemoMeeting: week1

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1. Legend

1.1. Priority Importance indicators

1.1.1. High Priority

1.1.2. Medium Priority

1.1.3. Low Priority

1.2. Flags and Icons

1.2.1. Flags

1.2.2. Icons

1.3. Task Completion indicators

1.3.1. Not Started

1.3.2. 25% complete

1.3.3. 50% complete

1.3.4. 75% complete

1.3.5. Done

2. Participants

2.1. Quy Truong

2.2. Cuong Pham

3. Goals

3.1. Understand PCI express standard

3.1.1. overview of PCIe architecture: (transaction layer, data link layer, physical layer)

3.1.2. transaction layer

3.1.3. data link layer

3.1.4. physical layer logical sub-block byte striping logic / byte de-striping logic scramber/de-scramber 8b10b encoder/decoder serialize/deserialize muxer electrical sub-lock question? received/transmit clock recovery PLL Initialization and training deadline 19-Oct Clock recovering

3.1.5. references: PCIe spec 2.1, PCIe system architecture

3.2. Master Xilinx ISE design suite

3.2.1. installation on home-machine (ok) on company-machine (ok) fake time to use the expried licenses install on virtual-machine

3.2.2. develop some basic blocks and synthesize them using Xilinx ISE synthesis basic blocks by Xilinx XST simulate them by Mentor Questasim chose Plan Ahead TCL tool flow create/open a project design entry: import design synthesis design export the synthesized design post-synthesis simulation next plan basic block library 8b10b encoder/decoder

3.3. Try Xilinx-provided PCIe controller

3.4. Try/Find Xilinx-provided PCIe driver

3.4.1. Try/Find Xilinx-provided dirver VC705, VC707, VC709 sample projects

3.4.2. Try Matlab's Data acquisition toolbox

3.5. Design our own PCIe controller

3.5.1. create basic block library write the DTI_LIB blocks' wrappers implement our own blocks' cores test our own basic-block library simulate the Dynamo-Memory-Controller family using our own basic block library

3.5.2. create the testbench reference model

4. Notes

5. time: from August 26th to August 31st