1. Dual-Mode Operation
1.1. In order to ensure the proper execution of the operating system, the computer system must be able to distinguish between the execution of operating system code and user-defined code.
1.2. Provide hardware support to differentiate between at least two modes of operations.
2. Modes of Operation
2.1. User Mode
2.1.1. user program executes in user mode
2.1.2. certain areas of memory are protected from user access
2.1.3. certain instructions may not be executed
2.2. Kernel Mode
2.2.1. monitor executes in kernel mode
2.2.2. privileged instructions may be executed
2.2.3. protected areas of memory may be accessed
3. I/O Protection
3.1. All I/O instructions are privileged instructions; user program cannot issue I/O instructions directly.
3.2. Must ensure that a user program could never gain control of the computer in monitor mode
4. Memory Protection
4.1. computer system must provide memory protection at least for the interrupt vector and the interrupt service routines.
4.2. Base register
4.2.1. holds the smallest legal physical memory address.
4.3. Limit register
4.3.1. contains the size of the range
5. Hardware Address Protection
5.1. When executing in kernel mode, the operating system has unrestricted access to both monitor and user’s memory.
5.2. The load instructions for the base and limit registers are privileged instructions.
6. CPU Protection
6.1. Timer
6.1.1. interrupts computer after specified period to ensure operating system maintains control over CPU.
6.2. When timer interrupts, control transfers to the operating system.
6.3. Load-timer is a privileged instruction.
7. Computer-System Operation
7.1. A general-purpose computer system consists of one or more CPUs and a number of device controllers.
7.2. Each device controller is in charge of a specific type of device.
7.3. Each device controller has a local buffer.
7.4. The CPU and device controllers can execute concurrently.
7.5. Device controller informs CPU that it has finished its operation by causing an interrupt.
7.6. Interrupt indicates the occurrence of an event from either the hardware or software.
8. Interrupt Handling
8.1. When the CPU is interrupted, it stops what it is doing and immediately transfers execution to a fixed location.
8.1.1. fixed location contains the starting address of the interrupt service routine.
8.2. Interrupt vector provide the address of the interrupt service routine for the interrupting device.
8.3. Separate segments of code determine what action should be taken for each type of interrupt.
8.4. The OS preserves the state of the CPU by storing registers and the program counter.
8.5. After the interrupt is serviced, the saved return address is loaded into the program counter.
8.5.1. The interrupted computation resumes.
9. Synchronous I/O Structure
9.1. After I/O starts, control returns to user program only upon I/O completion.
9.1.1. Wait instruction idles the CPU until the next interrupt
9.1.2. Wait loop (contention for memory access).
9.1.3. At most one I/O request is outstanding at a time, no simultaneous I/O processing.
10. Asynchronous I/O Structure
10.1. After I/O starts, control returns to user program without waiting for I/O completion.
10.1.1. System call
10.1.1.1. request to the operating system to allow user to wait for I/O completion.
10.2. Device-status table contains entry for each I/O device Indicating its type, address, and state.
10.3. Operating system indexes into I/O device table to determine device status and to modify table entry to Include interrupt.
11. Storage Structure
11.1. Main memory
11.1.1. only large storage media that the CPU can access directly.
11.1.1.1. volatile storage device that loses its contents when power is turned off.
11.2. Secondary storage
11.2.1. extension of main memory that provides nonvolatile storage capacity.
11.2.1.1. It is capable to hold large quantities of data permanently
12. Storage Hierarchy
12.1. Storage systems organized in hierarchy.
12.1.1. Speed
12.1.2. Cost
12.1.3. Volatility
12.2. Caching
12.2.1. copying information into faster storage system; main memory can be viewed as a last cache for secondary storage.