8-bit RISC based CPU
von Klaus Aschenbrenner
1. Timer
1.1. NE555
1.2. Ripple Counter
1.3. 3-to-8 Decoder
1.4. Stop Circuit
2. System Buses
2.1. 8-bit Data Bus
2.2. 16-bit Address Bus
2.3. Flags Bus
3. 8-bit ALU
3.1. Interface
3.1.1. Input A
3.1.2. Input B
3.1.3. Output C
3.1.4. Internal A
3.2. Operations
3.2.1. NOP
3.2.2. XOR
3.2.3. OR
3.2.4. AND
3.2.5. ADD
3.2.6. NOT
3.2.7. SHL
3.2.8. ADC
3.2.9. SUB
3.2.10. NEG
3.2.11. SBB
3.2.12. RCL
3.2.13. SHR
3.2.14. SAR
3.2.15. RCR
3.2.16. MOV8
4. Instruction Decoder
4.1. FETCH/INCREMENT
4.2. ALU
4.2.1. SETAB
4.2.2. MOV_ALU_IN
4.2.3. ALU
4.2.4. MOV_ALU_OUT
4.3. MOV
4.3.1. MOV
4.3.2. MOV16
4.4. Memory Access
4.4.1. LOAD
4.4.2. STORE
4.5. Flags
4.5.1. STORE_FLAGS
4.5.2. LOAD_FLAGS
4.5.3. SAVE_FLAGS
4.5.4. RESTORE_FLAGS
4.5.5. FLAGS_TO_OUTBUFFER
4.5.6. INBUFFER_TO_FLAGS
4.6. Jumps
4.6.1. JMP
4.6.2. JZ
4.6.3. JNS
4.6.4. JNC
4.6.5. JNZ
4.6.6. 16BIT_ADDER
4.7. IO
4.7.1. IN
4.7.2. OUT
4.8. HLT
5. General Purpose Registers
5.1. 8-bit Register
5.1.1. D
5.1.2. E
5.1.3. F
5.1.4. G
5.1.5. H
5.1.6. XL
5.1.7. XH
5.1.8. XE
5.2. 16-bit Register
5.2.1. M
5.2.2. X
5.2.3. J
5.2.4. SP
5.2.5. BP
5.2.6. PC
5.2.7. INC
5.2.8. Y
5.2.9. Z