Chapter 8: Memory Management

1. Paging

1.1. Address Translation Scheme

1.2. Address Translation Architecture

1.3. Paging Example

1.4. Free Frames

1.5. Implementation of Page Table

1.6. Associative Memory

1.7. Paging Hardware With TLB

1.8. Effective Access Time

1.9. Memory Protection

1.10. Valid (v) or Invalid (i) Bit In A Page Table

1.11. Page Table Structure

1.11.1. Hierarchical Paging

1.11.1.1. Two-Level Paging Example

1.11.1.2. Two-Level Page-Table Scheme

1.11.1.3. Address-Translation Scheme

1.11.2. Hashed Page Table

1.11.3. Inverted Page Table

1.11.3.1. Inverted Page Table Architecture

1.12. Shared Pages

1.13. Shared Pages Example

2. Segmentation

2.1. User's View of a Program

2.2. Logical View of Segmentation

2.3. Segmentation Architecture

2.4. Address Translation Architecture

2.5. Example of Segmentation

2.6. Sharing of Segments

3. Segmentation with paging

3.1. MULTICS

3.1.1. MULTICS Address Translation Scheme

3.2. Intel 386

3.2.1. Intel 30386 Address Translation

3.3. Linux on Intel 80x86

4. Background

4.1. Binding of Instructions and Data to Memory

4.2. Multistep Processing of a User Program

4.3. Logical vs. Physical Address Space

4.4. Memory Management Unit

4.5. Dynamic relocation using a relocation register

4.6. Dynamic Loading

4.7. Dynamic Linking

5. Swapping

5.1. Schematic View of Swapping

6. Contiguous Allocation

6.1. Single-partition allocation

6.2. A base and a limit register define a logical address space

6.3. HW address protection with base and limit registers

6.4. Multiple-partition allocation

6.5. Dynamic Storage Allocation Problem

6.6. Fragmentation (Internal and External)