ARCHITECTURE OF ARM PROCESSOR
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1. Memory can be conceptually viewed as contiguous storage elements that hold data each element holding a fixed number of bits and having an address.
2. They have 4 classes of ISA
2.1. Stack (Emebedded processor)
2.2. Accumulator (Emebedded processor)
2.2.1. Defines data transfer modes (instructions) between registers, memory and I/O
2.3. Register - memory (pentium)
2.4. Register - Register (Spark)
3. Memory Organization and Addressing
3.1. The ARM core consists of 32 bits, meaning that you could address bytes in memory from address 0 to 2^32-1 or 4,294,967,295 (0xFFFFFFFF), which is considered to be 4GB of memory space.
3.2. A memory map is a structure of data (which usually resides in memory itself) that indicates how memory is laid out.
3.3. RISC architectures are considered to be load/store architectures, meaning that data in external memory must be brought into the processor using an instruction.
3.4. Load instruction take a single value from memory and write it to a general purpose register and store it to memory.
3.5. Store instructions read a value from a general-purpose register and store it to memory.
3.6. Load and store instruction : LDR|STR|{<size>}{<cond>}<Rd>,<addressing_mode>
3.7. The term effective address is often used to describe the final address created from values in the various registers, with offsets and/or shifts.
4. Instruction Set Architecture (ISA)
4.1. Instruction set of a computer: the portion of the computer visible to the assembly level programmer or to the compiler writer ISA
4.1.1. Defines registers
4.1.2. There should be sufficient instructions to efficiently translate any program
5. Operation modes of the cortex-M3 = The cortex-M3 processor has two modes and two privileged levels when is (thread modes and handler mode) is to determine whether the processor is running a normal program or running an exception handler like an interrupt handler or system exception handler like an interrupt handler or system exception handler.
6. Processor's Core Architecture
6.1. ARM core contains functional units (data path components) connected by data, address and control buses.
6.2. Data enters the processor core through the data bus.
6.3. The instruction decoder translates instructions before they are executed.
6.4. ARM implemented using Von Neumann architecture - data items and instructions share the same bus.
6.5. In contrast, ARM implemented on Harvard architecture implementations use two different buses.
6.6. The ARM processor uses load-store architecture.
6.6.1. Load instructions copy data from memory to registers in the core.
6.6.2. Store instructions copy data from registers to memory.