1. I/O Structure
1.1. Synchronous
1.1.1. after I/O starts, control return to user program only upon I/O completion
1.1.1.1. wait instruction idles the CPU until the next interrupt
1.1.1.2. wait loop(contention for memory access
1.1.1.3. I/O request is outstanding at a time, no simultaneous I/O processing
1.2. Asynchronous
1.2.1. after I/O starts, control return to user program without waiting for I/O completion
1.2.1.1. System call
1.2.1.1.1. request to the operating system to allow user to wait for I/O completion
1.2.1.2. Device
1.2.1.2.1. status table contains entry for each I/O device indicating its type, address and state
1.2.1.3. OS indexes into I/O device table to determine device status and to modify table entry to include interrupt
2. Storage structure/Storage hierarchy
2.1. Main memory
2.1.1. only large storage media that the CPU can access directly
2.1.2. a volatile storage device that loses its contents when power is turned off
2.2. Secondary storage
2.2.1. extension of main memory that provides nonvolatile storage capacity
2.2.2. it is capable to hold large quantities of data permanently
2.3. Organized in hierarchy
2.3.1. 1. speed 2. cost 3. volatility
2.4. caching
2.4.1. copying information into faster storage system
2.4.2. main memory can be viewed as a last cache for secondary storage
3. Dual-mode operation
3.1. distinguish between the execution of OS code and user-defined code
3.2. provide hardware support
3.3. modes of operation
3.3.1. user-mode
3.3.1.1. user program executes in user mode
3.3.1.2. certain areas of memory are protected from user access
3.3.1.3. certain instructions may not be executed
3.3.1.4. indicate current mode: 0
3.3.2. Kernel mode
3.3.2.1. monitor executes in kernel mode
3.3.2.2. privileged instruction may be executed
3.3.2.3. protected areas of memory may be accessed
3.3.2.4. indicates current mode : 1
4. Memory Protection
4.1. provide at least for the interrupt vector and the interrupt service routines
4.2. two registers are used to determine the range of legal addresses a program may access
4.2.1. base register
4.2.2. limit register
4.3. memory outside the defines range is protected
5. Computer System operation
5.1. consists of one or more CPUs and a number of device controllers
5.1.1. in charge of specific type of device
5.1.2. has a local buffer
5.1.3. execute concurrently
5.1.4. controller informs CPU that it has finished its operation by causing an interrupt
5.1.4.1. indicates the occurrence of an event from either hardware or software
6. Interrupt Handling
6.1. CPU interrupts, it stops what it is doing and immediately transfer execution to a fixed location
6.1.1. contains the starting address of the interrupt service routine
6.2. Interrupts vector provide the address of the interrupt service routine
6.3. separate segment of codes determine what action should be taken
6.4. OS preserves the state of the CPU by storing registers and the program counter
6.5. after being serviced, the saved return address is loaded into the program counter
6.5.1. interrupt computation resume
7. I/O Protection
7.1. privileged instruction
7.1.1. user program cannot issues I/O instruction directly
7.1.2. user program must executes system call to request that the operating system to perform I/O
7.2. ensure user program will not gain control of the computer in monitor mode
8. CPU Protection
8.1. Timer
8.1.1. interrupts computer after specified period to ensure OS maintains control over CPU
8.1.2. counter decremented every the clock ticks
8.1.3. interrupts occur when timer reaches 0
8.1.4. when interrupts, control transfer to OS
8.1.5. load timer is a privileged instruction