Chapter 2 Computer System Structures

1. Interrupt Handling

1.1. 1. CPU interrupted -> stop what it's doing -> transfer execution to interrupt vector table

1.2. 2. interrupt vector provide address of interrupt service routine for interrupting device

1.3. 3. separate segments -> determine what action should be taken for the interrupt

1.4. 4. OS save the state of CPU ->saved return address is loaded into program counter

1.5. 5. interrupt already serviced -> saved return address is loaded into program counter

1.6. 6. interrupted computation resumes

2. Synchronous I/O Structure

2.1. CPU do nothing when instruction running

2.2. only allow 1 instruction run at the time

3. Asynchronous I/O Structure

3.1. CPU can do other thing -> can fully utilize

3.2. can return the control to the user while processing

4. Dual-Mode Operation

4.1. User Mode

4.2. Kernel Mode

5. Memory Protection

5.1. Interrupt vector & interrupt service routines must have memory protection

5.2. Base register - Holds smallest legal physical memory address

5.3. Limit register - contain the size of the range

6. CPU Protection

6.1. Timer - when timer reaches value 0, interrupt occurs

6.2. To prevent CPU from getting stuck in infinite loops