1. CLO
1.1. Apply the knowledge of logic operations using Boolean Algebra or Karnaugh Map in digital logic circuit ( C3 , PLO 1 )
1.2. Construct the logic diagrams, truth tables and timing diagrams using logic gates and flip-flop ( P4 , PLO 5 )
1.3. Demonstrate ability to work as individual and collaborative in team to complete assigned task during practical work sessions ( A3 , PLO 8 )
2. Continuous Assessment (CA)
2.1. Theory Test (1)
2.1.1. 15%
2.2. Practical Work (6)
2.2.1. 30%
2.3. Practical Work (Generic Scill)
2.3.1. 5%
2.4. EOC (1)
2.4.1. 10%
3. Final Exam
3.1. Structure (80m)
3.1.1. Number and codes (T1)
3.1.2. BOOLEAN OPERATIONS AND DATA PROCESSING CIRCUIT (T2) & Flip Flop (T3)
3.1.3. Flip-flops (T3) & Counters (T4)
3.1.4. Counters (T4) & Registers (T5)
3.2. Essay(20m)
3.2.1. :bomb: BOOLEAN OPERATIONS AND DATA PROCESSING CIRCUIT (T2))
4. References
4.1. Neal S. Widmer, Gregory L. Moss, Ronald J. Tocci (2017). Digital Systems-Principles and Applications (12th ed.). Pearson Higher Ed USA.
4.2. Roger Tokheim, Patrick E. Hoppe (2022). Digital Electronics: Principles and Applications (Ninth Edition). McGraw Hill LLC USA.
4.3. Dhanasekharan Natarajan (2021). Fundamentals of Digital Electronics. Springer Nature Switzerland.
4.4. Dr. B.R. Gupta, V. Singhal (2021). Digital Electronics (5th edition). S.K. Kataria & Sons.
4.5. Dr. Sanjay Sharma (2022). Digital Electronics and Logic Design (4th edition). S.K. Kataria & Sons.
4.6. Floyd, L. Thomas (2014). Digital Fundamentals (11th ed.). Pearson Education International.
5. PLO
5.1. PLO1: apply knowledge of applied mathematics, applied science, engineering fundamentals and an engineering specialisation as specified in DK1 to DK4 respectively to wide practical procedures and practices
5.2. PLO5: Apply appropriate techniques, resources, and modern engineering computing and IT tools to well defined engineering problems, with an awareness of the limitations (DK2 and DK6)
5.3. PLO8: Function effectively as an individual, and as a member in diverse and inclusive teams in multi-disciplinary, face to face, remote and distributed settings (DK9)
6. Sub Topics
6.1. Numbers & Codes
6.1.1. Numbers
6.1.1.1. DECIMAL
6.1.1.1.1. N10-N2,8,16
6.1.1.2. BINARY
6.1.1.2.1. N2-N8,10,16
6.1.1.3. OCTAL
6.1.1.3.1. N8-N2,10,16
6.1.1.4. HEXADECIMAL
6.1.1.4.1. N16-N2,10,8
6.1.2. Codes
6.1.2.1. BCD
6.1.2.1.1. BCD-N10-N2
6.1.2.2. ASCII
6.1.2.3. GRAY
6.1.2.3.1. GRAY-N2
6.1.3. Arithmetics
6.1.3.1. Addition
6.1.3.2. Substract
6.1.4. Complements
6.1.4.1. 1st complement
6.1.4.2. 2nd complement
6.2. BOOLEAN OPERATIONS AND DATA PROCESSING CIRCUIT :
6.2.1. Gates
6.2.1.1. Basic Gates
6.2.1.1.1. NOT
6.2.1.1.2. AND
6.2.1.1.3. OR
6.2.1.2. Universal Gates
6.2.1.2.1. NOR
6.2.1.2.2. NAND
6.2.1.2.3. EX OR
6.2.1.2.4. EX NOR
6.2.2. Draw logic circuit using NAND gate
6.2.3. Logic Circuit
6.2.3.1. SOP
6.2.3.2. POS
6.2.4. Simplified
6.2.4.1. Boolean
6.2.4.2. K-Maps
6.2.4.3. De' Morgan
6.2.5. Data Processing Circuit
6.2.5.1. Encoder
6.2.5.2. Decoder
6.2.5.3. Multiplexer
6.2.5.4. Demultiplexer
6.3. FLip-Flops
6.3.1. Asychronous
6.3.1.1. SR Flip-Flops
6.3.1.1.1. SR NOR
6.3.1.1.2. SR NAND
6.3.2. Sycnhronous
6.3.2.1. Clocked SR
6.3.2.2. JK
6.3.2.3. D
6.3.2.4. T
6.3.2.5. JK with Preset & Clr
6.3.3. Application
6.3.3.1. Memory
6.3.3.2. Logic Controller
6.3.3.3. Counter
6.3.3.4. Register
6.4. Counters
6.4.1. Asynchronous
6.4.1.1. Up Counter
6.4.1.2. Down Counter
6.4.1.3. Up/Down Counter
6.4.1.4. Decade Counter
6.4.1.5. Modulo <2n
6.4.2. Synchronous
6.4.2.1. Up Counter
6.4.2.2. Down Counter
6.4.2.3. Up/Down Counter
6.4.2.4. Random Counter
6.4.3. Cascade
6.4.4. Application
6.5. Registers
6.5.1. Types
6.5.1.1. Series in Series Out (SISO)
6.5.1.2. Series in Parallel Out (SIPO)
6.5.1.3. Parallel In Parallel Out (PIPO)
6.5.1.4. Parallel In Series Out (PISO)
6.5.2. Application
6.5.2.1. Arithmetic
6.5.2.1.1. Multiplier
6.5.2.1.2. Divider
6.5.2.2. Counter
6.5.2.2.1. Ring Counter
6.5.2.2.2. Johnson Counter