1. Computer System Operation
1.1. Memory Controller
1.1.1. In charge of a specific type of device.
1.2. Execute concurrently
1.3. Interrupt indicates the occurrence of an event from either the hardware or software
1.4. Device controller
1.4.1. To synchronize the access to the memory.
2. Interrupt Handling
2.1. Different codes determine which action should be done for each interrupt.
2.2. Interrupt service routine
2.2.1. Part of the operating system which takes action in response to the condition that caused the interrput.
2.3. OS preserves the state of the CPU by storing registers and program counter.
2.4. Interrupt vector provide the address of the interrupt service routine for interrupting device.
3. Two I/O module
3.1. Asynchronous I/O Structure
3.1.1. Controls returns to user program without waiting for I/O completion.
3.1.2. Device-status table
3.1.2.1. Contains entry for each I/O device indicating its type, address and state.
3.1.3. system call
3.1.3.1. Request OS to allow user to wait for I/O completion.
3.2. Synchronous I/O Structure
3.2.1. Only upon I/O completion controls is returns to user programs
3.2.2. Only one I/O request is outstanding at a time, no simultaneous I/O processing.
4. Storage Structure
4.1. Main memory
4.1.1. Only large storage media that CPU can access directly.
4.1.2. Volatile storage
4.2. Storage Hierarchy
4.2.1. Organize in hierarchy based on:
4.2.1.1. Speed
4.2.1.2. Cost
4.2.1.3. Volatibility
4.2.2. Caching
4.2.3. Electronic disc
4.2.3.1. Store data in memory (volatile)
4.2.3.2. Data can be copied to non-volatile if power is interrupted.
4.3. Secondary storage
4.3.1. Extension of main memory that provides nonvolatile storage.
5. Dual-mode Operation
5.1. Provide hardware support to differentiate between two modes of operation.
5.2. User Mode (1)
5.2.1. executes user program
5.2.2. certain areas of memory is protected from user access
5.2.3. certain instructions may not be executes
5.3. kernel mode (0)
5.3.1. monitor executes in kernel mode
5.3.2. privileged instructions will run only in this mode
5.3.3. protected area of memory is accessable
5.4. Hardware switch to kernel mode when interrupt or fault occurs.
6. I/O protection
6.1. All I/o instructions are privileged instructions
6.2. User program cannot issue I/O instructions directly
6.3. Ensure user cannot gain control in monitor mode.---
7. Memory protection
7.1. Base register
7.1.1. holds the smallest legal physical memory address
7.2. Limit register
7.2.1. contains the size of range
7.3. Memory outside the defined range is protected.
8. Hardware address protection
8.1. Instructions for base and limit registers are privileged insructions
9. CPU Protection
9.1. Load-timer is a privileged instruction
9.2. Timer
9.2.1. interrupts computer after certain period to ensure the controls of OS over CPU