DCS5058 - OPERATING SYSTEMS (CHAPER 2)

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DCS5058 - OPERATING SYSTEMS (CHAPER 2) by Mind Map: DCS5058 - OPERATING SYSTEMS (CHAPER 2)

1. Modes of Operation

1.1. User Mode

1.1.1. *User program executes in User Mode *Certain areas of memory are protected from user access. *Certain instructions may not be executed.

1.2. Karnel Mode

1.2.1. *Monitor executes in Karnel Mode *Protected areas of memory may be accessed. *Privileged instruction may be executed.

2. Computer System Operation

2.1. A general-purpose computer system consists of one or more CPUs and a number of device controllers.  Each device controller is in charge of a specific type of device.  Each device controller has a local buffer.  The CPU and device controllers can execute concurrently.  Device controller informs CPU that it has finished its operation by causing an interrupt.  Interrupt indicates the occurrence of an event from either the hardware or software.

3. Interrupt Handling

3.1. *CPU Interrupted: - It stop what it is doing - Transfer execution to a fixed location (contains the starting address of the interruptservice routine) *Interrupt vector:- provide the address of the interrupt service routine for the interrupting device. *Separate Segments Code: - What action should be taken *OS Presrves :- Storing registers and the program counter After the interrupt is serviced :- the saved return address is loaded into the program counter.

4. Storage Structure

4.1. Main Memory

4.2. only large storage media that the cpu can access directly.

4.3. Volatile Storagedevice

4.4. loses its contents when power is turned off

4.5. Secondary Storage

4.6. extension of main memory that provides nonvolatile storage capacity

5. Storage Hierarchy

5.1. Speed

5.2. Cost

5.3. Volatility

5.4. Caching

5.4.1. Copying information into faster storage system.

6. I/O Structure

6.1. Synchronous

6.1.1. After I/O starts: 1) Control returns to user program only upon I/O completion. 2) wait instruction idles the cpu until the next interrupt 3) Wait loop --> contention for memory access) 4) A most one I/O request is outstanding at a time, no simultaneous I/O processing

6.2. Asynchronous

6.2.1. After I/O starts: 1) Control returns to user program without waiting for I/O completion. 2) System Call --> Request to OS to allow user to wait for I/O completion. 3) Device-status --> contains entry for each I/O device indicating its type, address and state. 4) OS --> Indexs into I/O device table to determine device status --> To modify table entry to include interrupt.

7. Dual-Mode Operation

7.1. Proper execution of the OS, the computer Sys. must able to distinguish between the execution of OS code and user-defined code.

7.2. Hardware support to differentiate between at least two modes of operations.

7.3. Computer Hardware indicate the current mode; Kernel (O)/ User (I).

7.4. Interrupt/ Fault Occurs, Hardware switches to kernel mode.

7.5. Privileged instructions can be issued only monitor mode.

7.6. Kernel Mode : software has complete control of the processor and all instruction, registers and memory.

7.7. This level of control is not necessary and for safety is not desirable for user programs.

8. Protection

8.1. I/O

8.1.1. User program must executes a system call to request that the OS to preform I/O

8.1.2. All I/O instruction are privileged instructions;

8.1.2.1. user program cannot issue I/O instructions directly

8.1.3. Ensure that a user program could never gain control of the computer in monitor mode.

8.2. Memory

8.2.1. The computer sys must provide memory protection at least for the interrupt vector and the interrupt service routines.

8.2.2. Two Register --> to determine the range of legel addresses program.

8.2.2.1. Base Register : Holds the smallest legal physical memory address.

8.2.2.2. Limit Register : Contains the sice of the range

8.2.3. Memory Outside the defines range is protected.

8.3. Hardware Address

8.3.1. Kernel Mode : the OS has unrestricted access to both monitor and user's memory.

8.3.1.1. OS is allowed to load user's programs into user's memory, to access and modify parameters of system calls.

8.3.2. The load instructions for the base and limit registers are privileged instruction.

8.4. CPU

8.4.1. Timer : interrupts computer after specified period to ensure OS maintains control over CPU

8.4.2. When timer interrupts, control transfer to the OS.

8.4.3. Load-Timer is a privileged instruction.